1. Field
Embodiments of the invention relate to the field of booting a computing device; and more specifically, to the booting of a computing device from flash memory, such as NAND flash memory.
2. Background
Flash memory is a non-volatile memory that is a specific type of EEPROM (Electrical Erasable Programmable Read-Only Memory) semiconductor memory. There are generally two commonly used types of flash memory that are in use: NOR flash and NAND flash. Typically, a NAND flash memory is less expensive, has higher capacity, and has faster program and erase times, than that of a NOR flash memory. For this reason, NAND flash is commonly used in computing devices for data storage (e.g., media players, cellular telephones, smart mobile phones, thumb drives, digital cameras, computers, etc.).
NAND flash memory is error prone. Thus, an error correction algorithm must be performed when writing data to the NAND flash memory and when reading data from the NAND flash memory. A NAND flash memory is organized into blocks and further organized into pages. The page size of a NAND flash memory varies between manufacturer and the variety of flash memory, but generally ranges from 512 bytes to 4,096 bytes. A block may be, for example, 32 pages of 512 bytes, or 64 pages of 2048 bytes. Each page is typically split between a large data area portion to store data, and a smaller spare area portion used to store error correction parity information, bad block management, etc. For example, a page of size 2112 bytes is typically split between a 2048 byte data area and a 64 byte spare area. The amount of data space required for error correction typically depends on the page size of the NAND flash memory and the particular error correction algorithm chosen. For example, a NAND flash memory with a large page size requires an error correction algorithm that produces a large amount of error correction parity information; whereas a NAND flash memory with a smaller page size requires an error correction algorithm that produces a smaller amount of error correction parity information.
There is no standard for accessing all varieties of NAND flash memories. Thus, different manufacturers of NAND flash memories, and even different NAND flash models within a manufacturer, may require different commands and/or variations of commands, to access those NAND flash memories. To handle these differences, typically a NAND flash identification table is maintained on the computing device. For example, in a typical method to boot from a NAND flash memory, the computing device must be aware of parametric information of the NAND flash memory (e.g., error correction configuration (e.g., type, parity size), device addressing (e.g., size of pages read from the NAND flash memory), I/O signal timing, etc.). Due to the variable nature of NAND flash memory (e.g., no standard command interface to the NAND flash memory), the parametric information cannot be automatically determined by the computing device (e.g., through interrogating the device as if it were a standard hard disk) without additional hardware or software employed in the computing device. Thus, typically the computing device stores a parametric table of known NAND flash memories (identifiable by the manufacturer and flash memory ID) that may act as boot devices in a read only memory (ROM) that is not changed after it has been written. During the boot up process, the computing device determines the parametric information of the NAND flash from the parametric table and, among other things, configures the read routine to access the NAND memory based on the information in the parametric table. Since the NAND flash parametric table is stored in ROM, any change to the flash parametric table requires a replacement of the ROM. Thus, any new NAND flash memories that are developed once the parametric table is written to the ROM cannot be used in the boot up process (e.g., they will not have entries in the parametric table).
Additionally, the product cycle of a NAND flash memory is typically faster than that of the ROM storing the parametric table. In other words, in a typical computing device booting from a NAND flash, the ROM is programmed with the NAND flash parametric table before a NAND device is selected for use in the computing device. Thus, a NAND device may be selected that is not included in the NAND flash parametric table (e.g., if the type of NAND device was manufactured at a later time than when the ROM was programmed) and thus cannot be used as the boot device.